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? semiconductor components industries, llc, 2015 july, 2015 ? rev. 9 1 publication order number: ncp451/d ncp451 3a ultra-small low ron and controlled load switch with auto-discharge path the ncp451 is a very low ron mosfet controlled by external logic pin, allowing optimization of battery life, and portable device autonomy. indeed, due to a current consumption optimization with nmos structure, leakage currents are eliminated by isolating connected ic on the battery when not used. output discharge path is also embedded to eliminate residual voltages on the output rail. proposed in a wide input voltage range from 0.75 v to 5.5 v, in a small 0.9 x 1.4 mm wlcsp6, pitch 0.5 mm. features ? 0.75 v ? 5.5 v operating range ? 12 m n mosfet from 3.6 v to 5.5 v ? 13 m n mosfet from 1 v to 3.3 v ? dc current up to 3 a ? output auto?discharge ? active high en pin ? wlcsp6 0.9 x 1.4 mm ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? mobile phones ? tablets ? digital cameras ? gps ? portable devices www. onsemi.com see detailed ordering, marking and shipping information on page 10 of this data sheet. ordering information (top view) pinout diagram a b c 12 out in out in gnd en wlcsp6 fc suffix case 499br marking diagram xxxx ayww xxxx = specific device code a = assembly location y = year ww = work week = pb?free package wlcsp6 afc suffix case 567kb xxxx ayww
ncp451 www. onsemi.com 2 enx en 0 dcdc converter v+ platform ic?n ls ldo or ncp451 in a2 in b2 gnd c1 en c2 out b1 out a1 figure 1. typical application circuit pin function description pin name pin number type description in a2, b2 power load?switch input voltage; connect a 1 f or greater ceramic capacitor from in to gnd as close as possible to the ic. gnd c1 power ground connection. en c2 input enable input, logic high turns on power switch. out a1, b1 output load?switch output; connect a 1 f ceramic capacitor from out to gnd as close as possible to the ic is recommended. block diagram en block control logic charge pump and soft start control in: pin a2, b2 en: pin c2 out: pin a1, b1 gnd: pin c1 figure 2. block diagram
ncp451 www. onsemi.com 3 maximum ratings symbol rating value unit in, out, en, pins: (note 1) v en, v in, v out ?0.3 to + 7.0 v from in to out pins: input/output (note 1) v in, v out 0 to + 7.0 v human body model (hbm) esd rating are (notes 1 and 2) esd hbm 1.5 kv machine model (mm) esd rating are (notes 1 and 2) esd mm 250 v charge device model (cdm) esd rating are (notes 1 and 2) esd cdm 2000 v latch?up protection (note 3) ?pins in, out, en lu 100 ma maximum junction temperature t j ?40 to + 125 c storage temperature range t stg ?40 to + 150 c moisture sensitivity (note 4) msl level 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. according to jedec standard jesd22?a108. 2. this device series contains esd protection and passes the following tests: human body model (hbm) 1.5 kv per jedec standard: jesd22?a114 for all pins. machine model (mm) 250 v per jedec standard: jesd22?a115 for all pins. charge device model (cdm) 2.0 kv per jedec standard: jesd22?c101 for all pins. 3. latchup current maximum rating: 100 ma per jedec standard: jesd78 class ii. 4. moisture sensitivity level (msl): 1 per ipc/jedec standard: j?std?020. operating conditions symbol parameter conditions min typ max unit v in operational power supply 0.75 5.5 v v en enable voltage 0 5.5 v t a ambient temperature range ?40 25 +85 c t j junction temperature range ?40 25 +125 c c in decoupling input capacitor 1 f c out decoupling output capacitor 1 f r ja thermal resistance junction to air (note 5) 100 c/w i out maximum dc current 3 a p d power dissipation rating (note 6) over temperature 0.315 w functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 5. the r ja is dependent of the pcb heat dissipation and thermal via. 6. the maximum power dissipation (p d ) is given by the following formula: p d t jmax t a r ja
ncp451 www. onsemi.com 4 electrical characteristics min & max limits apply for t a between ?40 c to +85 c for v in between 0.75 v to 5.0 v (unless otherwise noted). typical values are referenced to t a = + 25 c and v in = 3.6 v (unless otherwise noted). symbol parameter conditions min typ max unit power switch r ds(on) static drain?source on?state resistance v in = 5 v i out = 200 ma, t a = 25 c 12 20 m t j = 125 c 25 v in = 3.6 v i out = 200 ma, t a = 25 c 12 20 t j = 125 c 25 v in = 3.3 v i out = 200 ma, t a = 25 c 13 24 t j = 125 c 28 v in = 2.5 v i out = 200 ma, t a = 25 c 13 24 t j = 125 c 28 v in = 1.8 v i out = 200 ma, t a = 25 c 13 24 t j = 125 c 28 v in = 1.0 v i out = 200 ma, t a = 25 c 13 24 t j = 125 c 28 v in = 0.75 v i out = 200 ma, t a = 25 c 15 28 t j = 125 c 35 rdis output discharge path en = low ncp451 1.2 1.7 m ncp451a 1.0 1.7 k v ih high?level input voltage 0.8 v v il low?level input voltage 0. 4 i en en pin leakage current v in = 3.6 v 0.1 a quiescent current istd standby current v in = 4.2 v en = low, no load 0.9 2 a iq quiescent current v in = 3.6 v v in = 2.5 v v in = 1.8 v v in = 1.2 v v in = 1.0 v v in = 0.75 v en = high, no load (note 7) 8 15 a timings t en enable time v in = 3.6 v (note 8) r l = 25 , c out = 1 f 600 s t r output rise time r l = 25 , c out = 1 f 800 t on on time (t en + t r) r l = 25 , c out = 1 f 1400 t f output fall time r l = 25 , c out = 1 f 55 timings t en enable time v in = 3.6 v (note 8) r l = 10 , c out = 0.1 f 540 s t r output rise time r l = 10 , c out = 0.1 f 670 t on on time (t en + t r) r l = 10 , c out = 0.1 f 1210 t f output fall time r l = 10 , c out = 0.1 f 2.5 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 7. production tested at v in = 3.6 v. 8. parameters are guaranteed for c load and r load connected to the out pin with respect to the ground
ncp451 www. onsemi.com 5 timings figure 3. enable, rise and fall time v in en v out t en t r t on t f
ncp451 www. onsemi.com 6 electrical curves figure 4. r ds(on) vs. v in , low load 20 19 18 17 16 15 14 13 12 11 10 v in (v) r ds(on) (m ) 1.5 0.5 1.0 2.0 5.5 5.0 4.5 4.0 2.5 3.0 3.5 25 v in (v) r ds(on) (m ) 1.5 0.5 1.0 2.0 5.5 5.0 4.5 4.0 2.5 3.0 3.5 figure 5. r ds(on) vs. v in , low load, multi temperature 20 15 10 5 ?40 c 0 c 50 c ?25 c 25 c 85 c v in = 5.5 v v in = 4.2 v v in = 3.3 v v in = 1.8 v v in = 0.75 v v in = 5 v v in = 3.6 v v in = 2.5 v v in = 1.0 v 30 junction temperature ( c) r ds(on) (m ) ?50 25 20 15 10 5 0 ?25 0 25 125 100 50 75 figure 6. r ds(on) vs. temperature, multi v in voltage 3.0 v in (v) i in ( a) 06 2.5 2.0 1.5 1.0 0.5 0 12345 ?40 c 25 c 85 c figure 7. standby current ( a) vs. temperature ?40 c 25 c 85 c 125 c 20 v in (v) i in ( a) 0 16 12 8 6 2 0 12 6 5 34 figure 8. quiescent current ( a) vs. temperature ?40 c25 c 85 c 3.0 v in (v) i in ( a) 06 2.5 2.0 1.5 1.0 0.5 0 12345 3.5 figure 9. mosfet leakage current ( a) vs. temperature 4 10 14 18
ncp451 www. onsemi.com 7 electrical curves figure 10. en pin leakage vs. temperature v en = v in = 5.5 v v en = v in = 3.6 v junction temperature ( c) i enleak (na) ?50 4 2 0 ?25 0 25 125 100 50 75
ncp451 www. onsemi.com 8 functional description overview the ncp451 is a high side n channel mosfet power distribution switch designed to isolate ics connected on the battery in order to save energy. the part can be turned on, with a wide range of battery from 0.75 v to 5.5 v. enable input enable pin is an active high. the path is opened when en pin is tied low (disable), forcing n?mosfet switch off. the in/out path is activated with a minimum of vin of 0.75 v and en forced to high level. auto discharge n?mosfet is placed between the output pin and gnd, in order to discharge the application capacitor connected on out pin. the auto?discharge is activated when en pin is set to low level (disable state). the discharge path (pull down nmos) stays activated as long as en pin is set at low level and v in > 0.75 v. in order to limit the current across the internal discharge n?mosfet, the typical value is set at r dis . c in and c out capacitors in and out, 1 f, at least, capacitors must be placed as close as possible the part to for stability improvement. application information power dissipation main contributor in term of junction temperature is the power dissipation of the power mosfet. assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: p d r ds(on) i out 2 p d = power dissipation (w) r ds(on) = power mosfet on resistance ( ) i out = output current (a) t j p d r ja t a t j = junction temperature ( c) r ja = package thermal resistance ( c/w) t a = ambient temperature ( c) pcb recommendations the ncp451 integrates an up to 3 a rated nmos fet, and the pcb design rules must be respected to properly evacuate the heat out of the silicon. by increasing pcb area, especially around in and out pins, the r ja of the package can be decreased, allowing higher power dissipation. routing example: 2 oz, 4 layers with vias across 2 internal inners. figure 11. example of application definition. t j t a r ja r ds(on) i 2 t j : junction temperature. t a : ambient temperature. rtheta= thermal resistance between ic and air, through pcb. r ds(on) : intrinsic resistance of the ic mosfet. i: load dc current.
ncp451 www. onsemi.com 9 taking into account of rtheta obtain with: 1 oz, 2 layers: 100 c/w. at 3 a, 25 c ambient temperature, r ds(on) 20 m @ v in 5 v, the junction temperature will be: t j t a rtheta p d 25 0.02 3 3 100 43 c taking into account of rtheta obtain with: 2 oz, 4 layers: 60 c/w. at 3 a, 65 c ambient temperature, r ds(on) 24 m @ v in 5 v, the junction temperature will be: t j t a rtheta p d 65 0.024 3 2 60 78 c figure 12. demoboard pcb top view figure 13. demoboard pcb top view out2 gnd 1 2 input2 c1 en out1 gnd 1 2 d1 diode zener1 d2 diode zener1 input1 r1 100 k r2 100 k c2 gnd1 gnd gnd2 gnd3 u1 ncp451 in a2 in b2 gnd c1 en c2 out b1 out a1 figure 14. demobard schematic
ncp451 www. onsemi.com 10 quantity reference scheme part description part number manufacturer 2 in, out socket, 4mm, metal, pk5 b010 hirschmann 3 in_2, out_2, , en header200 2.54 mm, 77313?101?06lf fc 3 c1, c2 1uf grm155r70j105ka12# murata 1 d1, d2 tvs (not mounted) esd9x on semiconductor 2 gnd2,gnd gnd jumper d3082f05 harvin 2 r2, r3 resistor 100k 0603 mc 0.063 0603 1% 100k multicomp 1 u1 load switch ncp451 on semiconductor bill of material ordering information device marking option package shipping ? ncp451fct2g 451 auto discharge 1.2 m case 499br (pb?free) 3000 / tape & reel ncp451afct2g 51a auto discharge 1.0 k case 567kb* (pb?free) 3000 / tape & reel NCP451AFCCT2G 51ac auto discharge 1.0 k with chipcoat case 567kb* (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *ubm = 205 m ( 8 m)
ncp451 www. onsemi.com 11 package dimensions wlcsp6, 1.40x0.90 case 567kb issue a seating plane 0.25 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min nom ??? millimeters a1 d e b 0.195 ??? e 0.50 bsc ??? d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 6x b abc 1 2 0.10 c a a1 a2 c 0.142 ??? 0.25 c 2x top view side view bottom view note 3 e a2 pitch 0.25 6x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 0.50 recommended a1 package outline pitch e/2 ??? 0.320 ??? 1.400 ??? 0.900 0.235 0.510 0.172 0.338 1.440 0.940 max
ncp451 www. onsemi.com 12 package dimensions case 499br issue a seating plane 0.25 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 d 1.40 bsc e b 0.21 0.25 e 0.50 bsc 0.50 d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 6x b abc 1 2 0.10 c a a1 a2 c 0.17 0.23 0.90 bsc 0.25 c 2x top view side view bottom view note 3 e a2 0.25 ref pitch 0.25 6x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 0.50 recommended a1 package outline pitch e/2 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp451/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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